Note: Page numbers followed by b indicate boxes, f indicate figures and t indicate tables.
A
Acorn RISC Machine (ARM) processor
8–9
in decimal and binary
173b
American Standard Code for Information Interchange (ASCII)
control characters
20,
21t
converting character strings to ASCII codes
21–23,
23t,
24t
interpreting data as ASCII strings
23–24,
24t
Arithmetic and logic unit (ALU)
54–55
Arithmetic instructions, ARM
83–85
Arithmetic instructions, NEON
335–343
add vector elements pairwise
338–339
select maximum/minimum elements
341–342
vector addition and subtraction
335–337
for loop re-written as a post-test loop
107–108
reverse function implementation
121–122
ARM condition modifiers
59t
ARM instruction set architecture
95–96
data processing instructions
79–80
arithmetic operations
83–85
comparison operations
81–82
data movement operations
86–87
division operations
89–90
multiply operations with 32-bit results
87–88
multiply operations with 64-bit results
88–89
pseudo-instructions, ARM
93
accessing CPSR and SPSR
91
load/store instructions
60–61
exclusive load/store
69–70
ARM user program registers
112f
Atomic Energy of Canada Limited (AECL)
161–162
B
factorial function calculation
212
64-bit functions, signed and unsigned
190
32-bit functions, signed and unsigned
190
Binary tree, of word frequency
151f
non-terminating, repeating
223b
Bitwise logical operations, NEON
326–327
Branch instructions, ARM processor
70
C
Central processing unit (CPU)
components and data paths
54–55
array of structured data
127
calling
scanf and
printf 110
using recursion to reverse a string
120–121
Clock Control Unit (CCU)
409
Compilation sequence
5,
6f
Complex Instruction Set Computing (CISC) processor
8
conversion between arbitrary bases
13b
decimal to base b
12,
13b
excess-(2
n−−1–1) representation
16
sign-magnitude representation
15
Conditional assembly
46–47
ARM assembly implementation
251,
257
battery powered systems
260
double precision software float C
259
double precision VFP C
260
factorial terms, formats and constants for
249–251
intermediate calculations
251
performance implementations
259t
single precision software float C
259
single precision VFP C
259
32-bit fixed point assembly
259
Current Program Status Register (CPSR)
57–58
D
Data conversion instructions
fixed point and single-precision
321–322
half-precision and single-precision
322
fixed point to single precision
284–285
Data movement instructions
change size of elements in vector
311–312
moving between NEON scalar and integer register
309–310
ARM register and VFP system register
282
VFP register and one integer register
280–281
VFP register and two integer registers
281
Data processing instructions, ARM
79–80
arithmetic operations
83–85
comparison operations
81–82
data movement operations
86–87
division operations
89–90
with 64-bit results
88–89
with 32-bit results
87–88
mathematical operations
278
Data register, Raspberry Pi UART
413,
414t
Data section, memory
28–29
to arbitrary base, conversion
220–223
64-bit functions, signed and unsigned
190
32-bit functions, signed and unsigned
190
in decimal and binary
181f
floating point operation
247
maintaining precision
236
of variable by constant
193
clock management device
408t
divisor latch high register
424,
425t
divisor latch low register
424,
424t
Double-precision floating point number
E
with multiple user processes
436,
437f
F
FIFO control register
425t
maintaining precision
236
Floating-point Exception register (FPEXC)
274
Floating point operations
Floating Point Status and Control Register (FPSCR)
268–273
Floating-point System ID register (FPSID)
274
Fractional baud rate divisor
414,
416t
Fractional numbers, base conversion
223–225
arbitrary base to decimal
220
Fused multiply accumulate operation
346
G
GPIO pin event detect status registers
382
GPIO pin pull-up/down registers
381–382
parallel printer port
377
detecting GPIO events
390
enabling internal pull-up/pull-down
389–390
function select code assignments
392t
header pin assignments
391f
reading and setting GPIO pins
388–389
pin function select bits
380t
detecting GPIO events
382
enabling internal pull-up/pull-down
381–382
GPIO pins available on
382
header pin assignments
384f
reading GPIO input pins
381
Generic Interrupt Controller (GIC) device
449–451
GNU assembler (GAS)
35,
40
allocating space for variables and constants
41–43,
42f
conditional assembly
46–47
current section selection
40–41
filling and aligning
43–45
including other source files
47–48
setting and manipulating symbols
45–47
assembler directives
36–38
assembly instructions
36,
38
H
Half-precision floating point number
structured data type
73–74
Hindu-Arabic number system
9–10
I
data movement NEON instructions
310–311
Instruction components
58
setting and using condition flags
58–59,
58t
Instruction set architecture (ISA)
53
Integer baud rate divisor
414,
416t
subtraction by addition
172
moving between NEON scalar and
309–310
Interrupt clear register
418
Interrupt-driven program
461
Interrupt enable register
429
Interrupt Identity Register
429
Interrupt mask set/clear register
417
L
Least significant bit (LSB)
11
Linux, accessing devices under
365–376
Load and store instructions
60–61
exclusive load/store
69–70
load copies of structure to all lanes
305–307
M
Macros, GNU assembly directives
48–50
Masked interrupt status register
418
Mathematical operations, VFP
278
hardware address mapping for
366f
Modem Control Register
429
Modem Scratch Register
429
Modem Status Register
429
Monostable multivibrator
400
Most significant bit (MSB)
11
in decimal and binary
174b
floating point operation
247
fused multiply accumulate
346
saturating multiply and double
347–348
Multistage noise shaping (MASH) filtering
407
N
add vector elements pairwise
338–339
select maximum/minimum elements
341–342
vector addition and subtraction
335–337
fixed point and single-precision
321–322
half-precision and single-precision
322
change size of elements in vector
311–312
moving between NEON scalar and integer register
309–310
load and store instructions
302–309
multiplication and division
343–351
fused multiply accumulate
346
saturating multiply and double
347–348
bitwise logical operations with immediate data
352–353
saturating shift right by immediate
332–333
shift left/right by variable
330–331
user program registers
300f
for improving reciprocal estimates
349–350
quad-precision, IEEE 754
246
single-precision, IEEE 754
245
floating point operations
multiplication and division
247
fractional numbers, base conversion
arbitrary base to decimal
220
factorial terms, formats and constants
249–251
using fixed-point calculations
257
O
P
Parallel communications
409
enabling internal pull-up/pull-down
389–390
function select code assignments
392t
header pin assignments
391f
reading and setting GPIO pins
388–389
user program memory space on
372,
376
control register bits
402t
divisor latch high register
424,
425t
divisor latch low register
424,
424t
FIFO control register
425t
interrupt enable register
429
Interrupt Identity Register
429
Modem Control Register
429
Modem Scratch Register
429
Modem Status Register
429
receive FIFO level register
426,
428t
transmit FIFO level register
426,
428t
transmit holding register
424,
424t
Program Status Register (PSR)
433–434
Pseudo-instructions, ARM processor
73,
93
bitwise logical operations with immediate data
352–353
Pulse density modulation (PDM)
396,
396f
Pulse frequency modulation (PFM)
396,
396f
Pulse width modulation (PWM)
397,
397f
Q
Quad-precision floating point number
246
R
Radix ten Hindu-Arabic system
10
enabling internal pull-up/pull-down
381–382
header pin assignments
384f
pin alternate functions
385t
user program memory on
372
interrupt controllers
441,
451
control register bits
399t
assembly functions for
422
fractional baud rate divisor
414,
416t
integer baud rate divisor
414,
416t
interrupt clear register
418
interrupt mask set/clear register
417
line control register bits
416,
416t
masked interrupt status register
418
raw interrupt status register
418
receive status register/error clear register
414,
415t
Raw interrupt status register
418
Receive buffer register, UART
423,
424t
Receive FIFO level register, UART
426,
428t
Receive status register/error clear register
414,
415t
Reduced Instruction Set Computing (RISC) processor
8
S
Saved Process Status Register (SPSR)
432–433
divisor latch high register
424,
425t
divisor latch low register
424,
424t
FIFO control register
425t
receive FIFO level register
426,
428t
transmit FIFO level register
426,
428t
transmit holding register
424,
424t
assembly functions for
422
fractional baud rate divisor
414,
416t
integer baud rate divisor
414,
416t
line control register bits
416,
416t
receive status register/error clear register
414,
415t
Serial Peripheral Interface (SPI) functions
382
saturating shift right by immediate
332–333
shift left/right by variable
330–331
ARM assembly implementation
251,
257
battery powered systems
260
double precision software float C
259
double precision VFP C
260
factorial terms, formats and constants for
249–251
intermediate calculations
251
performance implementations
259t
single precision software float C
259
single precision VFP C
259
32-bit fixed point assembly
259
vector implementation
289,
291
Single instruction multiple data (SIMD) instructions
5
Single-precision floating point number
Special instructions, ARM
accessing CPSR and SPSR
91
Stack and Heap segments
28–29
using branch instructions
102
using conditional execution
101–102
standard C library functions
110
in decimal and binary
173b
T
Text section, memory
28–29
double pass accelerator
161
Three address instruction
80
Transmit FIFO level register
426,
428t
Transmit holding register
424,
424t
U
UCS Transformation Format-8-bit (UTF-8)
26–27
Universal Asynchronous Receiver/Transmitter (UART)
410–412
divisor latch high register
424,
425t
divisor latch low register
424,
424t
FIFO control register
425t
receive FIFO level register
426,
428t
transmit FIFO level register
426,
428t
transmit holding register
424,
424t
assembly functions for
422
fractional baud rate divisor
414,
416t
integer baud rate divisor
414,
416t
line control register bits
416,
416t
receive status register/error clear register
414,
415t
transmitter and receiver timings for
411f
Universal Character Set (UCS) code
26
V
Vector floating point (VFP)
data conversion instructions
282–285
data movement instructions between
279–282
ARM register and VFP system register
282
VFP register and one integer register
280–281
VFP register and two integer register
281
data processing instructions
277–279
mathematical operations
278
load and store instructions
274–277
user program registers
267f
W
wl_print_numerical function
147–150
Word frequency counts, ADT
Z