4.1.1 Operand2

Most of the data processing instructions require the programmer to specify two source operands and one destination register for the result. Because three items must be specified for these instructions, they are known as three address instructions. The use of the word address in this case has nothing to do with memory addresses. The term three address instruction comes from earlier processor architectures that allow arithmetic operations to be performed with data that is stored in memory rather than registers. The first source operand specifies a register whose contents will be on the A bus in Fig. 3.1. The second source operand will be on the B bus and is referred to as Operand2. Operand2 can be any one of the following three things:

• a register (r0-r15),

• a register (r0-r15) and a shift operation to modify it, or

• a 32-bit immediate value that can be constructed by shifting, rotating, and/or complementing an 8-bit value.

The options for Operand2 allow a great deal of flexibility. Many operations that would require two instructions on most processors can be performed using a single ARM instruction. Table 4.1 shows the mnemonics used for specifying shift operations, which we refer to as < shift_op >.

Table 4.1

Shift and rotate operations in Operand2

The lsl operation shifts each bit left by a specified amount n. Zero is shifted into the n least significant bits, and the most significant n bits are lost. The lsr operation shifts each bit right by a specified amount n. Zero is shifted into the n most significant bits, and the least significant n bits are lost. The asr operation shifts each bit right by a specified amount n. The n most significant bits become copies of the sign bit (bit 31), and the least significant n bits are lost. The ror operation rotates each bit right by a specified amount n. The n most significant bits become the least significant n bits. The RRX operation rotates one place to the right but the CPSR carry flag, C, is included. The carry flag and the register together create a 33 bit quantity to be rotated. The carry flag is rotated into the most significant bit of the register, and the least significant bit of the register is rotated into the carry flag. Table 4.2 shows all of the possible forms for Operand2.

4.1.2 Comparison Operations

These four comparison operations update the CPSR flags, but have no other effect:

cmp Compare,

cmn Compare Negative,

tst Test Bits, and

teq Test Equivalence.

They each perform an arithmetic operation, but the result of the operation is discarded. Only the CPSR carry flags are affected.

Examples

Example 4.1 shows how conditional execution and the test instruction can be used together to create an if-then-else structure. Note that in this case, the assembly code is more concise than the C code. That is not generally true.

Example 4.1

Making an If-Then-Else Construct

The following C code adds three to a if a is odd, and adds seven to a if a is even.

Assuming that the value of a is currently being stored in register r4, the following ARM assembly code performs the same function:

4.1.3 Arithmetic Operations

There are six basic arithmetic operations:

add Add,

adc Add with Carry,

sub Subtract,

sbc Subtract with Carry,

rsb Reverse Subtract, and

rsc Reverse Subtract with Carry.

All of them involve two 32-bit source operands and a destination register.

Operations

Name	Effect	Description
add	$Rd\leftarrow Rn+operand2$	Add
adc	$Rd\leftarrow Rn+operand2+carry$	Add with carry
sub	$Rd\leftarrow Rn-operand2$	Subtract
sbc	$Rd\leftarrow Rn-operand2+carry-1$	Subtract with carry
rsb	$Rd\leftarrow operand2-Rn$	Reverse subtract
rsc	$Rd\leftarrow operand2-Rn+carry-1$	Reverse subtract with carry

Examples

Example 4.2 shows a complete program for adding the contents of two statically allocated variables and printing the result. The printf () function expects to find the address of a string in r0. As it prints the string, it finds the \%d formatting command, which indicates that the value of an integer variable should be printed. It expects the variable to be stored in r1. Note that the variable sum does not need to be stored in memory. It is stored in r1, where printf () expects to find it.

Example 4.2

Adding the Contents of Two Variables

The following C program will add together two numbers stored in memory and print the result.

The equivalent ARM assembly program is as follows:

Example 4.3 shows how the compare, branch, and add instructions can be used to create a loop. There are basically three steps for creating a loop: allocating and initializing the loop variable, testing the loop variable, and modifying the loop variable. In general, any of the registers r0-r12 can be used to hold the loop variable. Section 5.4 introduces some considerations for choosing an appropriate register. For now, it is assumed that r0 is available for use as the loop variable for this example.

Example 4.3

Making a Loop

Suppose we want to implement a loop that is equivalent to the following C code:

The loop can be written with the following ARM assembly code:

4.1.4 Logical Operations

There are five basic logical operations:

and Bitwise AND,

orr Bitwise OR,

eor Bitwise Exclusive OR,

orn Bitwise OR NOT, and

bic Bit Clear.

All of them involve two source operands and a destination register.

Operations

Name	Effect	Description
and	$Rd\leftarrow Rn\wedge operand2$	Bitwise AND
orr	$Rd\leftarrow Rn\vee operand2$	Bitwise OR
eor	$Rd\leftarrow Rn\oplus operand2$	Bitwise Exclusive OR
orn	$Rd\leftarrow \neg (Rn\vee operand2)$	Complement of Bitwise OR
bic	$Rd\leftarrow Rn\wedge \neg operand2$	Bit Clear

Examples

4.1.5 Data Movement Operations

The data movement operations copy data from one register to another:

mov Move,

mvn Move Not, and

movt Move Top.

The movt instruction copies 16 bits of data into the upper 16 bits of the destination register, without affecting the lower 16 bits. It is available on ARMv6T2 and newer processors.

Operations

Name	Effect	Description
mov	$Rd\leftarrow operand2$	Copy operand2 to Rd
mvn	$Rn\leftarrow \neg operand2$	Copy 1’s complement of operand2
movt	$Rn\leftarrow (immed16\ll 16)\vee (Rd\wedge 0xFFFF)$	Copy immed16 into upper 16 bits of Rd

Examples

4.1.6 Multiply Operations with 32-bit Results

These two instructions perform multiplication using two 32-bit registers to form a 32-bit result:

mul Multiply, and

mla Multiply and Accumulate.

The mla instruction adds a third register to the result of the multiplication.

Operations

Name	Effect	Description
mul	$Rd\leftarrow Rm\times Rs$	Multiply
mla	$Rd\leftarrow Rm\times Rs+Rn$	Multiply and accumulate

Examples

4.1.7 Multiply Operations with 64-bit Results

These instructions perform multiplication using two 32-bit registers to form a 64-bit result:

smull Signed Multiply Long,

umull Unsigned Multiply Long,

smlal Signed Multiply and Accumulate Long, and

umlal Unsigned Multiply and Accumulate Long.

The smlal and umlal instructions add a 64-bit quantity to the result of the multiplication.

Operations

Name	Effect	Description
smull	$RdHi:RdLo\leftarrow Rm\times Rs$	Signed Multiply
umull	$RdHi:RdLo\leftarrow Rm\times Rs$	Unsigned Multiply
smlal	$RdHi:RdLo\leftarrow Rm\times Rs+RdHi:RdLo$	Signed Multiply and Accumulate
umlal	$RdHi:RdLo\leftarrow Rm\times Rs+RdHi:RdLo$	Unsigned Multiply and Accumulate

Examples

4.1.8 Division Operations

Some ARM processors have the following instructions to perform division:

sdiv Signed Divide, and

udiv Unsigned Divide.

The divide operations are available on Cortex M3 and newer ARM processors. The processor used on the Raspberry Pi does not have these instructions. The Raspberry Pi 2 does have them.

Operations

Name	Effect	Description
sdiv	$Rd\leftarrow Rm÷Rn$	Signed Divide
udiv	$Rd\leftarrow Rm÷Rn$	Unsigned Divide

Examples

4.2.1 Count Leading Zeros

This instruction counts the number of leading zeros in the operand register and stores the result in the destination register:

clz Count Leading Zeros.

Operations

Name	Effect	Description
clz	$Rd\leftarrow 31-⌊lo{g}_2(Rm)⌋$	Count leading zeros in Rm

Example

4.2.2 Accessing the CPSR and SPSR

These two instructions allow the programmer to access the status bits of the CPSR and SPSR:

mrs Move Status to Register, and

msr Move Register to Status.

The SPSR is covered in Section 14.1.

Operations

Name	Effect	Description
mrs	$Rd\leftarrow CPSR|SPSR$	Move from Status Register
msr	$CPSR|SPSR\leftarrow Rn$	Move to Status Register

Examples

4.2.3 Software Interrupt

The following instruction allows a user program to perform a system call to request operating system services:

swi Software Interrupt.

In Unix and Linux, the system calls are documented in the second section of the online manual. Each system call has a unique id number which is defined in the /usr/include/syscall.h file.

Example

4.2.4 Thumb Mode

The ARM processor has an alternate mode where it executes a 16-bit instruction set known as Thumb. This instruction allows the programmer to change the processor mode and branch to Thumb code:

bx Branch and Exchange.

The thumb instruction set is sometimes more efficient than the full ARM instruction set, and may offer advantages on small systems.

Operations

Name	Effect	Description
bx	$\mathit{pc}\leftarrow \mathit{target\_address}$	Branch and change to ARM state. Bit 0 of Rn must be set to 1. Used to return from a Thumb subroutine
blx	$lr\leftarrow pc\vee 1$$\mathit{pc}\leftarrow \mathit{target\_address}$	Branch and link with change to Thumb state. Bit 0 of Rn must be set to 1. Bit 0 of lr will be set to 1

Example

4.3.1 No Operation

This pseudo instruction does nothing, but takes one clock cycle to execute.

nop No Operation.

This is equivalent to a mov r0,r0 instruction.

Examples

4.3.2 Shifts

These pseudo instructions are assembled into mov instructions with an appropriate shift of Operand2:

lsl Logical Shift Left,

lsr Logical Shift Right,

asr Arithmetic Shift Right,

ror Rotate Right, and

rrx Rotate Right with eXtend.

Operations

Name	Effect	Description
lsl	$Rd\leftarrow Rn\ll shift$	Shift Left
lsr	$Rd\leftarrow Rn\gg shift$	Shift Right
asr	$Rd\leftarrow Rn\gg shift$	Shift Right with sign extend
rrx	$Rd:Carry\leftarrow Carry:Rd$	Rotate Right with eXtend

The rrx operation rotates one place to the right but the CPSR carry flag, C, is included. The carry flag and the register together create a 33-bit quantity to be rotated. The carry flag is rotated into the most significant bit of the register, and the least significant bit of the register is rotated into the carry flag.

Examples