Yes, this is not a typo, there is sequential addressing when it comes to addressing data as well, although it does require certain setup.

Remember the RSI/RDI pair (or ESI/EDI for 32-bit systems), which we have mentioned in both Chapter 1, Intel Architecture, and Chapter 3, Intel Instruction Set Architecture (ISA). This pair is a good example of sequential data addressing, where the source and/or target addresses are incremented or decremented (depending on the value of the direction flag) automatically after each instruction that uses these registers (either one of them or both) has been executed.

The following example illustrates this mode by copying a text string from its location in the data section to a buffer allocated on the stack:

 ; This portion goes into the code section.
 ; Assuming the RBP register contains the stack frame address
 ; and the size of the frame is 0x50 bytes.
 lea rdi, [rbp – 0x50]
 lea rsi, [my_string]
 mov ecx, my_string_len
 rep movsb
 
 ; And this portion goes into the data section
 my_string db ‘Just some string’,0
 my_string_len = $ - my_string

As we see, the RDI register is loaded with the lowest address in the stack frame, the RSI register is loaded with the address of the string, and the RCX register is loaded with the length of the string, including the terminating zero. After that, each time the rep movsb line is executed, both the RSI and the RDI are sequentially incremented (the size of increment is dependent, as we remember, on the movs* variant--1 for movsb, 2 for movsw, 4 for movsd, and 8 for movsq on a 64-bit platform).